1. Technical Field
The present invention relates to latency reduction is a digitally controlled circuit and more particularly to a method and apparatus for latency reduction in digital phase locked loops (DPLLs) and digital delay locked loops (DDLLs).
2. Description of the Related Art
A proportional path is an important component of a proportional-integral-derivative (PID) controller. Digital PID controllers are used in digital phase locked loops (DPLL), digital delay locked loops (DDLL), hard disk drive read channels, and many other control systems. Note that application of the proportional control is not limited to PID controllers, it can be a part of a far more general control system. It is well known that delay in the proportional path is detrimental to the overall performance of the system.
In analog control systems (charge pump PLLs, for example), this problem is typically addressed by utilizing dual-loop controls with a high-bandwidth proportional path. In digitally controlled systems, like DPLL, the problem of lowering latency in the proportional path is particularly important since processing (weighting and applying) of the proportional control typically requires a few clock cycles. It should be noted that, unlike other components of the control system (the integral or differential paths, for example), the proportional path does not depend on the history of the error detector output.
FIG. 1 illustrates an example of a proportional-integral (PI) loop filter in a DPLL. A digital phase-frequency error signal (ERROR) is first multiplied by the weight “P” of a proportional path by a multiplier 12. Then, the output is combined by an adder 14 with an integral path control I which is multiplied by with ERROR by multiplier 16 and integrated by integrator 18. The combined output is optionally scaled (Gain) and is finally applied to a digitally controlled oscillator (DCO) 20.
Each of these operations requires one or more clock cycles and increases latency in the proportional path. Various techniques can be used to lower the latency of the digital blocks in the signal flow from the error input to the DCO controls. However, the state of the art approach inherently has non-zero latency which cannot be reduced below a certain limit.